DESIGN NAME: VTS
PRIMARY FUNCTION: Void Elimination Oven
INSPIRATION: VTS gives the ultimate void free solution for the past 5 decades engineer had been looking for. Not just quality is dramatically improved but also manufacturing mindset is turnover. The concept of "Less is More" is fulfilled by VTS realized combining the simplification of process in semiconductor assembly field and broaden the application window to make things get easier.
UNIQUE PROPERTIES / PROJECT DESCRIPTION: Efficiency, reliability, performance, breakthrough: the highlight on VTS (Void Terminator System) has been achieving real cost reduction by simplified process, enhanced product yield, it did overturn years of conventional working process in semiconductor assembly market. Dedicated for liquid resin encapsulation or Flip-Chip Capillary Underfill (CUF) process with the aim of reducing the total cost ownership(TCO) through void free solution and dispenser throughput. VTS improves overall process efficiency by means of yield performance.
OPERATION / FLOW / INTERACTION: Integrated ease of use User's Interface on 10 inch multiple touch screen, combine with predictive preventative protection and smart maintenance system.
PROJECT DURATION AND LOCATION: The VTS project started in 2014 in Taiwan, achieved the shipment first batch of products in January 2015 in Canada; and continuous achievement in 2015 in Europe and Taiwan.
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PRODUCTION / REALIZATION TECHNOLOGY: pulsed pressure modulation, fast ramp-up & cool-down rate of temperature, multi touch screen, EtherNet TCP/IP, SECS/GEM communication
SPECIFICATIONS / TECHNICAL PROPERTIES: Width 1000 mm x Depth 1650 mm x Height 1760 mm, compacted IPC by 10 inch multi touch screen with complete functionalities and essential software system are integrated.
TAGS: VTS, APT, Void Free, Cost Reduction, Process Simplification, Void Elimination, Capillary Underfill, Flip-Chip
RESEARCH ABSTRACT: With increasing needs for more I/Os and the miniaturization of electronics due to increased use of hand-held applications, flip chip packaging is encountering severe challenges as the pitch and gap are constantly shrinking. These challenges must be addressed in order to meet the higher reliability requirements and cost demands, so called Total Cost of Ownership (TCO) includes aforementioned and enhance process yield via decreasing process difficulties for mass production.
CHALLENGE: Getting more and more users choose not to keep wondering that is it real passing flux residue cleaning, carrier pre-baking and even plasma cleaning from typical Flip-Chip Capillary Underfill process? It's believed that VTS eventually brings crystal answers into the market.
ADDED DATE: 2016-03-04 13:51:13
TEAM MEMBERS (1) : APT FAE Division, APT R&D Division, APT Marketing Division
IMAGE CREDITS: AblePrint Technology, 2015.
PATENTS/COPYRIGHTS: US 7,863,094 B2 / AblePrint Technology Co., Ltd
US 8,936,968 B2 / AblePrint Technology Co., Ltd
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